demul1_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 25 行

--******************************************
--* 1 To 4  Demultiplexer (WHEN ... ELSE)  *
--*          Filename : DEMUL1_4           *
--******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEMUL1_4 is
    port (
          D: in STD_LOGIC;
          S: in STD_LOGIC_VECTOR (1 downto 0);
          Y: out STD_LOGIC_VECTOR (0 to 3)
         );
end DEMUL1_4;

architecture DEMUL1_4_arch of DEMUL1_4 is

begin
    Y(0) <= D when S = "00" else '0';
    Y(1) <= D when S = "01" else '0';
    Y(2) <= D when S = "10" else '0';
    Y(3) <= D when S = "11" else '0';
end DEMUL1_4_arch;