sh_ro.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.std_logic_1164.all;

entity SH_RO is
    port (
        DIN : in  BIT_VECTOR (7 downto 0);
        SLL1: out BIT_VECTOR (7 downto 0);
        SRL1: out BIT_VECTOR (7 downto 0);
        SRA1: out BIT_VECTOR (7 downto 0);
        SLA1: out BIT_VECTOR (7 downto 0);
        ROR1: out BIT_VECTOR (7 downto 0);
        ROL1: out BIT_VECTOR (7 downto 0);
        count: in integer range -4 to 3;
        CLK:  in std_logic
    );
end SH_RO;

architecture SH_RO_arch of SH_RO is


begin
     process (CLK)
     begin
     if rising_edge (CLK) then
     SLL1 <= DIN SLL COUNT;
     SRL1 <= DIN SRL COUNT;
     SRA1 <= DIN SRA COUNT;
     SLA1 <= DIN SLA COUNT;
     ROR1 <= DIN ROR COUNT;
     ROL1 <= DIN ROL COUNT;
     end if;
  end process;   
end SH_RO_arch;