ceven.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 41 行

--***********************************
--*   Counter 0,2,4,6,8,10,12,14    *
--*        Filename : CEVEN         *
--***********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity CEVEN is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     out STD_LOGIC_VECTOR (3 downto 0)
         );
end CEVEN;

architecture CEVEN_arch of CEVEN is
signal REG: std_logic_vector (3 downto 0);
begin
process (CLK,RESET,REG)

begin
    if RESET = '1' then 
       REG <= "0000";
    elsif CLK'event and CLK = '1' then
       case REG is
          when "0000" => REG <= "0010";
          when "0010" => REG <= "0100";
          when "0100" => REG <= "0110";
          when "0110" => REG <= "1000";
          when "1000" => REG <= "1010";
          when "1010" => REG <= "1100";
          when "1100" => REG <= "1110";
          when "1110" => REG <= "0000";
          when others => REG <= "0000";
       end case;
    end if;
end process;
Q <= REG;           
end CEVEN_arch;