rise_edg.prj

VHDL子程序集,包括各种例程资料以及源码.

Created by PCM: 6/22/102
Empty design C:\BOOK\RISE_EDG\RISE_EDG\rise_edg.EDF created: 6/22/102 [20.47.31].
'' saved on 02/06/22 20:52
'C:\BOOK\RISE_EDG\RISE_EDG\RISE_EDG.VHD' saved on 02/06/22 20:53
'C:\BOOK\RISE_EDG\RISE_EDG\RISE_EDG.VHD' saved on 02/06/22 20:57
'C:\BOOK\RISE_EDG\RISE_EDG\RISE_EDG.VHD' saved on 02/06/22 20:59
'C:\BOOK\RISE_EDG\RISE_EDG\RISE_EDG.VHD' saved on 02/06/22 21:00
'C:\BOOK\RISE_EDG\RISE_EDG\RISE_EDG.VHD' saved on 02/06/22 21:00
Document c:\book\rise_edg\rise_edg\rise_edg.vhd added: 6/22/102 [21.0.45].
Implementation ver1 updated: 6/22/102 [21.0.58].
Entity RISE_EDG, non optimized chip, file c:\book\rise_edg\rise_edg\rise_edg.vhd.Implementation ver1 updated: 6/22/102 [21.1.1].
Entity RISE_EDG, optimized chip ver1-Optimized, file c:\book\rise_edg\rise_edg\rise_edg.vhd.Implementation ver1 updated: 6/22/102 [21.1.2].
Entity RISE_EDG, optimized chip ver1-Optimized, file c:\book\rise_edg\rise_edg\rise_edg.vhd.'c:\book\rise_edg\rise_edg\rise_edg.vhd' saved on 02/07/15 02:19
'c:\book\rise_edg\rise_edg\rise_edg.vhd' saved on 02/08/02 17:05