rise_edg.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 35 行

--******************************
--*  D F/F With Synchronous    *
--*  Clear Using RISING_EDGE   *
--*    Filename : RISE_EDG     *
--******************************

library IEEE;
use IEEE.std_logic_1164.all;

entity RISE_EDG is
    port (
          D: in STD_LOGIC;
          CLK: in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q: out STD_LOGIC
         );
end RISE_EDG;

architecture RISE_EDG_arch of RISE_EDG is
   
begin
process (CLK,RESET)

begin
    if rising_edge (CLK) then
       if RESET = '0' then
          Q <= '0';
       else
          Q <= D;
       end if;   
    end if;
end process;

end RISE_EDG_arch;