wait1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 33 行

--*******************************
--*  D F/F With Synchronous     *
--*   Clear Using WAIT UNTIL    * 
--*       Filename : WAIT1      *
--*******************************

library IEEE;
use IEEE.std_logic_1164.all;

entity WAIT1 is
    port (
          D:     in STD_LOGIC;
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     out STD_LOGIC
         );
end WAIT1;

architecture WAIT1_arch of WAIT1 is
   
begin
process

begin
    if RESET = '0' then
       Q <= '0';
    end if;  
    wait until CLK'event and CLK = '0';
       Q <= D;
end process;

end WAIT1_arch;