wait1.out

来自「VHDL子程序集,包括各种例程资料以及源码.」· OUT 代码 · 共 20 行

Reading in the Synopsys vhdl primitives.
Warning: Clock signal is not in the sensitivity list.  "CLK" 
	in routine WAIT1 line 22 in file 'C:/book/wait1/wait1/wait1.vhd' (HDL-400)

Inferred memory devices in process 
	in routine WAIT1 line 22 in file
         'C:/book/wait1/wait1/wait1.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|        Q_reg        | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

Q_reg
-----
    set/reset/toggle: none


Writing to hnl file 'c:\BOOK\WAIT1\WAIT1\wait1/workdirs/WORK/WAIT1.hnl'