compon_3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 59 行

--**************************************
--*  1 To 8 Demultiplexer (Component)  * 
--* One 1 To 4 DEM and Four 1 To 2 DEM *
--*         Filename : COMPON_3        *
--**************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity COMPON_3 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (2 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 7)
         );
end COMPON_3;

architecture COMPON_3_arch of COMPON_3 is
signal X: STD_LOGIC_VECTOR(0 to 3); 

component DEM4_COM
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR ( 1 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 3)
         );
end component;
           
component DEM2_COM
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC;
          Y:   out STD_LOGIC_VECTOR (0 to 1)
         );
end component;
                           
begin
element1: DEM4_COM port map (
                   DIN => DIN,
                   S   => S(2 downto 1),
                   Y   => X);
element2: DEM2_COM port map (
                   DIN => X(0),
                   S   => S(0),
                   Y   => Y(0 to 1));
element3: DEM2_COM port map (
                  DIN => X(1),
                  S   => S(0),
                  Y   => Y(2 to 3));
element4: DEM2_COM port map (
                  DIN => X(2),
                  S   => S(0),
                  Y   => Y(4 to 5));
element5: DEM2_COM port map (
                  DIN => X(3),
                  S   => S(0),
                  Y   => Y(6 to 7));
end COMPON_3_arch;