proced_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 53 行

--*****************************************
--*   1 To 8 Demulptilexer (PROCEDURE)    *
--*  One 1 To 4 DEMUL Three 1 To 2 DEMUL  *
--*         Filename : PROCED_4           *
--*****************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity PROCED_4 is
    port (
          DIN :in STD_LOGIC;
          S   :in STD_LOGIC_VECTOR (2 downto 0);
          Y   :out STD_LOGIC_VECTOR (0 to 7)
         );
procedure DEMUL4
            (signal D :in std_logic;
             signal S :in std_logic_vector(1 downto 0);
             signal Y :out std_logic_vector(0 to 3)
            ) is
begin
    case S is
         when "00"   => Y <= D & "111";
         when "01"   => Y <= '1' & D & "11";
         when "10"   => Y <= "11" & D & '1';
         when others => Y <= "111" & D;
    end case;
end DEMUL4;

procedure DEMUL2
            (signal D :in std_logic;
             signal S :in std_logic;
             signal Y :out std_logic_vector(0 to 1)
            ) is  
begin
    case S is
         when '0'    => Y <= D & '1';
         when others => Y <= '1' & D;
    end case;
end DEMUL2;
                              
end PROCED_4;

architecture PROCED_4_arch of PROCED_4 is
signal X :std_logic_vector (0 to 3);
begin
    DEMUL4 (DIN,S(2 downto 1),X);
    DEMUL2 (X(0),S(0),Y(0 to 1));
    DEMUL2 (X(1),S(0),Y(2 to 3));
    DEMUL2 (X(2),S(0),Y(4 to 5));
    DEMUL2 (X(3),S(0),Y(6 to 7)); 
end PROCED_4_arch;