compon_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 47 行

--************************************
--*   1 Bit Full Adder (Component)   *
--*         Two Half Adder           *
--*       Filename : COMPON_4        *
--************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity COMPON_4 is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          C0: in STD_LOGIC;
          S0: out STD_LOGIC;
          C1: out STD_LOGIC
         );
end COMPON_4;

architecture COMPON_4_arch of COMPON_4 is
signal CT: STD_LOGIC;
signal ST: STD_LOGIC;
signal CA: STD_LOGIC;
 
component HA_COM
    port(
         X0: in STD_LOGIC;
         Y0: in STD_LOGIC;
         S0: out STD_LOGIC; 
         C1: out STD_LOGIC
        );
end component; 

component OR_GATE
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          F: out STD_LOGIC
         );
end component;
                      
begin
element1:HA_COM  port map (X0,Y0,ST,CT);
element2:HA_COM  port map (ST,C0,S0,CA);
element3:OR_GATE port map (CA,CT,C1);      
end COMPON_4_arch;