hadder.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 25 行

--***************************************
--*  Half Adder Using Boolean Algebra   *
--*         Filename : HADDER           *
--***************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity HADDER is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          S0: out STD_LOGIC;
          C1: out STD_LOGIC
         );
end HADDER;

architecture HADDER_arch of HADDER is

begin
    S0 <= X0 xor Y0;
    C1 <= X0 and Y0;
end HADDER_arch;