wait3.out

来自「VHDL子程序集,包括各种例程资料以及源码.」· OUT 代码 · 共 20 行

Reading in the Synopsys vhdl primitives.
Warning: Clock signal is not in the sensitivity list.  "CLK" 
	in routine WAIT3 line 24 in file 'C:/book/wait3/wait3/wait3.vhd' (HDL-400)

Inferred memory devices in process 
	in routine WAIT3 line 24 in file
         'C:/book/wait3/wait3/wait3.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|        Q_reg        | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Q_reg (width 2)
---------------
    set/reset/toggle: none


Writing to hnl file 'c:\BOOK\WAIT3\WAIT3\wait3/workdirs/WORK/WAIT3.hnl'