wait3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 38 行

--**************************************
--*  2 To 1 Multiplexer With Register  *
--* Synchronous Reset Using WAIT UNTIL *
--*           Filename : WAIT3         *
--**************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity WAIT3 is
    port (
          A:     in STD_LOGIC_VECTOR (0 to 1);
          B:     in STD_LOGIC_VECTOR (0 to 1);
          S:     in STD_LOGIC;
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC; 
          Q:     out STD_LOGIC_VECTOR (0 to 1)
         );
end WAIT3;

architecture WAIT3_arch of WAIT3 is

begin
process 

begin  
    wait until CLK'event and CLK = '1';
    if RESET = '0' then
       Q <= "00";
    elsif S = '0' then
       Q <= A;
    else
       Q <= B;
    end if;
end process;
                  
end WAIT3_arch;