dem1_4_s.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--*******************************************
--*  1 To 4 Demultiplexer (WITH .. SELECT)  *
--*          Filename : DEM1_4_S            *
--*******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEM1_4_S is
    port (
          DIN: in STD_LOGIC;
          Y:   out STD_LOGIC_VECTOR (0 to 3);
          S:   in STD_LOGIC_VECTOR (1 downto 0)
         );
end DEM1_4_S;

architecture DEM1_4_S_arch of DEM1_4_S is

begin
    with S select
       Y <= DIN & "111" when "00",
            '1' & DIN & "11" when "01",
            "11" & DIN & '1' when "10",
            "111" & DIN when others;
end DEM1_4_S_arch;