funct_2.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*************************************
--*    16 Bit Parity Even Generator   * 
--*        (FUNCTION IN ENTITY)       *  
--*  Two 8 Bit Parity Even Generator  * 
--*       Filename : FUNCT_2          * 
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity funct_2 is
    port (
          I:      in BIT_VECTOR (0 to 15);
          Parity: out BIT
         );
function even8 (
                I :bit_vector (0 to 7)
               ) return bit is
         variable PE: bit; 	 
 begin
     PE := '0';
     for K in I'left to I'right loop
         PE := PE xor I(K);
     end loop;
     return PE;
end even8;
 
end funct_2;

architecture funct_2_arch of funct_2 is

begin
    Parity <= even8 (I (0 to 7)) xor even8 (I (8 to 15)); 	  
end funct_2_arch;