funct_3.vhd

VHDL子程序集,包括各种例程资料以及源码.

--********************************************
--* 8 To 1 Multiplexer (FUNCTION IN ENTITY)  *
--*     Two 4 To 1 MUL And One 2 To 1 MUL    *
--*           Filename : FUNCT_3             *
--********************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity funct_3 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 7);
          S: in STD_LOGIC_VECTOR (2 downto 0);
          Y: out STD_LOGIC
         ); 
function MUL4 (
               I: std_logic_vector (0 to 3);
	       S: std_logic_vector (1 downto 0)
              ) return std_logic is 
         variable F: std_logic;
begin
    case S is
         when "00"   => F := I(0);
         when "01"   => F := I(1);
         when "10"   => F := I(2);
         when "11"   => F := I(3);
         when others => null;
    end case;
    return F;   
end MUL4;

function MUL2 (
               I: std_logic_vector (0 to 1);
               S: std_logic
              ) return std_logic is
         variable F: std_logic;
begin 
    case S is
         when '0'     => F := I(0);
         when '1'    => F := I(1);
         when others => null;
    end case;
    return F;   
end MUL2;

end funct_3;

architecture funct_3_arch of funct_3 is
signal result: std_logic_vector(0 to 1);
begin  
    result(1) <= MUL4 (I(4 to 7),S(1 downto 0));
    result(0) <= MUL4 (I(0 to 3),S(1 downto 0));
    Y         <= MUL2 (result,S(2));
end funct_3_arch;