mul2_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 22 行

--*************************
--*  1 To 2 Multiplexer   *
--*   Filename : MUL2_1   *
--*************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 1);
          S: in STD_LOGIC;
          F: out STD_LOGIC
         );
end MUL2_1;

architecture MUL2_1_arch of MUL2_1 is

begin
     F <= ((not S) and I(0)) or (S and I(1)); 
end MUL2_1_arch;