mul4_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 42 行

--**************************
--*   1 To 4 Multiplexer   *
--*    Filename : MUL4_1   *
--**************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity MUL4_1 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 3);
          S: in STD_LOGIC_VECTOR (1 downto 0);
          F: out STD_LOGIC
         );
end MUL4_1;

architecture MUL4_1_arch of MUL4_1 is

component MUL2_1
  port (
        I: in STD_LOGIC_VECTOR (0 to 1);
        S: in STD_LOGIC;
        F: out STD_LOGIC
       );
end component;        

signal X: STD_LOGIC_VECTOR (0 to 1);
begin
element1: MUL2_1 port map(
          I => I (0 to 1),
          S => S(0),
          F => X(0));
element2: MUL2_1 port map(
          I => I (2 to 3),
          S => S (0),
          F => X(1));
element3: MUL2_1 port map(
          I => X,
          S => S(1),
          F => F);                      
end MUL4_1_arch;