boolean0.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--*********************************
--*   2 To 4 Decoder Active LOW   *
--*   Using Boolean Algebra (0)   *
--*      Filename : BOOLEAN0      *
--********************************* 

library IEEE;
use IEEE.std_logic_1164.all;

entity BOOLEAN0 is
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          Y: out STD_LOGIC_VECTOR (0 to 3)
         );
end BOOLEAN0;

architecture BOOLEAN0_arch of BOOLEAN0 is

begin
    Y(0) <= not (not A and not B);
    Y(1) <= not (not A and B);
    Y(2) <= not (A and not B);
    Y(3) <= not (A and B); 
end BOOLEAN0_arch;