proced_5.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 37 行

--************************************
--*   16 Bit Parity ODD Generator    *
--*   (PROCEDUER IN ARCHITECTURE)    *
--*       Filename : PROCED_5        *
--************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity proced_5 is
    port (
          I:      in STD_LOGIC_VECTOR (0 to 15);
          Parity: out STD_LOGIC
         );
end proced_5;

architecture Proced_5_arch of Proced_5 is
signal X:std_logic_vector(1 downto 0);
 
procedure odd (signal I: in std_logic_vector ;
               signal P: out std_logic
              ) is
          variable PO:std_logic; 
begin 
    PO := '1';
    for K in i'range loop
        PO := PO xor I(K);
    end loop;
    P <= PO;
end odd;
   
begin
    odd (I(0 to 7),X(0));
    odd (I(8 to 15),X(1));
    Parity <= X(0) xnor X(1);
end proced_5_arch;