demul1_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 39 行

--********************************
--*   1 To 4 Demultiplexer   
--*    Filename : DEMUL1_4   
--********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEMUL1_4 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (1 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 3)
         );
end DEMUL1_4;

architecture DEMUL1_4_arch of DEMUL1_4 is

begin
process (DIN ,S)

begin
    if S(1) = '0' then
       if S(0) = '0' then
          Y <= DIN & "111";
       else
          Y <= '1' & DIN & "11";
       end if;
    else
       if S(0) = '0' then
          Y <= "11" & DIN & '1';
       else
          Y <= "111" & DIN;
       end if;
    end if;
end process; 
                       
end DEMUL1_4_arch;