compon_1.vhd

VHDL子程序集,包括各种例程资料以及源码.

--****************************************
--*  8 to 1 Multiplexer Using Component  *
--*  (Two 4 To 1 MUL And One 2 To 1MUL)  *   
--*        Filename : COMPON_1           *
--****************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity COMPON_1 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 7);
          S: in BIT_VECTOR (2 downto 0);
          Y: out STD_LOGIC
         );
end COMPON_1;

architecture COMPON_1_arch of COMPON_1 is

component MUL4_COM 
    port (
          I: in std_logic_vector (0 to 3);
          S: in BIT_VECTOR (1 downto 0);
          Y: out std_logic 
         );
end component;

component MUL2_COM    
    port (
          I: in std_logic_vector (0 to 1);
          S: in BIT;
          Y: out std_logic
         );
end component;

signal Y1,Y2 : std_logic;
begin
element1: MUL4_COM port map (
                   I(0) => I(0),
                   I(1) => I(1),
                   I(2) => I(2),
                   I(3) => I(3),
                   S    => S(1 downto 0),
                   Y    => Y1);
element2: MUL4_COM port map (
                   I(0) => I(4),
                   I(1) => I(5),
                   I(2) => I(6),
                   I(3) => I(7),
                   S    => S(1 downto 0),
                   Y    => Y2);
element3: MUL2_COM port map (
                   I(0) => Y1,
                   I(1) => Y2,
                   S    => S(2),
                   Y    => Y);
end COMPON_1_arch;