mul4_com.vhd

VHDL子程序集,包括各种例程资料以及源码.

--****************************
--*  Component Of COMPON_1   *
--*    4 To 1 Multiplexer    *
--*   Filename : MUL4_COM    *
--****************************
     
library IEEE;
use IEEE.std_logic_1164.all;

entity MUL4_COM is
    port (
          I: in STD_LOGIC_VECTOR (0 to 3);
          S: in BIT_VECTOR (1 downto 0);
          Y: out STD_LOGIC
         );
end MUL4_COM;

architecture MUL4_COM_arch of MUL4_COM is

begin
    Y <= I(0) when  S = "00" else
         I(1) when  S = "01" else
         I(2) when  S = "10" else
         I(3) ;
end MUL4_COM_arch;