proced_3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 37 行

--**************************************
--*  1 To 4 Demultiplexer (PROCEDURE)  *
--*    Three 1 To 2 Demultiplexer      *
--*        Filename : PROCED_3         *
--**************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity PROCED_3 is
    port (
          DIN :in STD_LOGIC;
          S   :in STD_LOGIC_vector (1 downto 0);
          Y   :out STD_LOGIC_VECTOR (0 to 3)
         );
end PROCED_3;

architecture PROCED_3_arch of PROCED_3 is
signal X:std_logic_vector (0 to 1);

procedure DEMUL2 (signal D :in std_logic;
                  signal S :in std_logic;
                  signal Y :out std_logic_vector (0 to 1) 
                 ) is 
begin
    case S is
         when '0'    => Y <= D & '0';
         when others => Y <= '0' & D;
    end case;
end DEMUL2;

begin
    DEMUL2 (DIN,S(1),X);
    DEMUL2 (X(0),S(0),Y(0 to 1));
    DEMUL2 (X(1),S(0),Y(2 to 3));
end PROCED_3_arch;