dff.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 29 行

--****************************************
--*  D Flip Flop With No Reset Clear  
--*          Filename : DFF           
--****************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
    port (
          D:   in STD_LOGIC;
          CLK: in STD_LOGIC;
          Q:   out STD_LOGIC
         );
end DFF;

architecture DFF_arch of DFF is

begin
process (CLK)

begin 
    if CLK'event and CLK = '1' then
       Q <= D;
    end if;
end process;
          
end DFF_arch;