fa_com.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 25 行

--**********************************
--*     Full Adder (COMPONENT)     *
--*        Filename : FA_COM       *
--**********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity FA_COM is
    port (
          X:    in STD_LOGIC;
          Y:    in STD_LOGIC;
          Cin:  in STD_LOGIC;
          S:    out STD_LOGIC;
          Cout: out STD_LOGIC
         );
end FA_COM;

architecture FA_COM_arch of FA_COM is

begin
    S    <= X xor Y xor Cin;
    Cout <= (X and Y) or (X and Cin) or (Y and Cin); 
end FA_COM_arch;