fa_4bit.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 39 行

--*************************************
--*    4 Bit Full Adder (GENERATE)    *
--*       One HA  and three FA        *
--*        Filename : FA_4BIT         *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity FA_4BIT is
    port (
          Cin: in STD_LOGIC;  
          X:   in STD_LOGIC_VECTOR (0 to 3);
          Y:   in STD_LOGIC_VECTOR (0 to 3);
          S:   out STD_LOGIC_VECTOR (0 to 4)
         );
end FA_4BIT;

architecture FA_4BIT_arch of FA_4BIT is
signal TEMP: std_logic_vector(0 to 4);

component FA_COM
       port (
             X:    in STD_LOGIC;
             Y:    in STD_LOGIC;
             Cin:  in STD_LOGIC; 
             S:    out STD_LOGIC;
             Cout: out STD_LOGIC
            );
end component;

begin
    TEMP(0) <= Cin;
LOP:for i in 0 to 3 generate
        FA:FA_COM port map (X(i),Y(i),TEMP(i),S(i),TEMP(I+1));
    end generate LOP;       
    S(4) <= TEMP (4);          
end FA_4BIT_arch;