gener_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 33 行

--******************************************
--*   16 Bit Gray Code To Binary Convert   *
--*     (GENERIC) Component : GRATOBIN     *
--*          Filename : GENER_4            *
--******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity GENER_4 is
    port (
          G: in    STD_LOGIC_VECTOR (0 to 15);
          B: inout STD_LOGIC_VECTOR (0 to 15)
         );
end GENER_4;

architecture GENER_4_arch of GENER_4 is

component GRATOBIN
        generic ( number: integer range 0 to 31);
        port
            ( 
             G: in    STD_LOGIC_VECTOR (0 to number - 1);
             B: inout STD_LOGIC_VECTOR (0 to number - 1)
             ); 
end component;
             
begin
Convert: GRATOBIN
         generic map (16)
         port map (G,B); 
end GENER_4_arch;