block_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 73 行

--*************************************
--*    8 To 1 Multiplexer (BLOCK)     *
--* Two 4 To 1 MUL and One 2 To 1 MUL *
--*         Filename : BLOCK_1        *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity BLOCK_1 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 7);
          S: in STD_LOGIC_VECTOR (2 downto 0);
          Y: out STD_LOGIC
         );
end BLOCK_1;

architecture BLOCK_1_arch of BLOCK_1 is
signal X: std_logic_vector (1 downto 0);
begin

MUL4_1:BLOCK

begin
process (S,I)
  
begin
    if S(1 downto 0) = "00" then
       X(0) <= I(0);
    elsif S(1 downto 0) = "01" then
       X(0) <= I(1);
    elsif S(1 downto 0) = "10" then
       X(0) <= I(2);
    else
       X(0) <= I(3);
    end if;
end process;

end BLOCK MUL4_1;

MUL4_2:BLOCK

begin
process (S,I)
  
begin
    case S(1 downto 0) is
        when "00"   => X(1) <= I(4);
        when "01"   => X(1) <= I(5);
        when "10"   => X(1) <= I(6);
        when others => X(1) <= I(7);
    end case;
end process;

end BLOCK MUL4_2;

MUL2:BLOCK

begin
process (S,X)
  
begin
    if S(2) = '0' then
       Y <= X(0);
    else
       Y <= X(1);
    end if;
end process;

end BLOCK MUL2;

end BLOCK_1_arch;