mul4_1_c.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 32 行

--*************************************
--*  4 TO 1 Multiplexer (CASE .. IS)  *
--*        Filename : MUL4_1_C        *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL4_1_C is
    port (
          I: in STD_LOGIC_VECTOR (0 to 3);
          S: in STD_LOGIC_VECTOR (1 downto 0);
          Y: out STD_LOGIC
         );
end MUL4_1_C;

architecture MUL4_1_C_arch of MUL4_1_C is

begin
process (S,I)

begin
    case S is
       when "00"   => Y <= I(0);
       when "01"   => Y <= I(1);
       when "10"   => Y <= I(2);
       when others => Y <= I(3);
    end case;	
end process; 
     
end MUL4_1_C_arch;