mul2_1_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 27 行

--****************************************
--* 2 To 1 Multiplexer Using Truth Table *
--*     Description (WITH ... SELECT)    *
--*         Filename : MUL2_1_4          *
--****************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_4 is
    port (
          S: in STD_LOGIC_VECTOR (2 downto 0);
          F: out STD_LOGIC
         );
end MUL2_1_4;

architecture MUL2_1_4_arch of MUL2_1_4 is

begin
    with S select
       F <= '1' when "010",
            '1' when "011",
            '1' when "101",
            '1' when "111",
            '0' when others;
end MUL2_1_4_arch;