compon_2.vhd

VHDL子程序集,包括各种例程资料以及源码.

--**************************************
--*  1 To 4 Demultiplexer (Component)  *
--*     Three 1 To 2 Demultiplexer     *
--*        Filename : COMPON_2         *
--**************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity COMPON_2 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (1 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 3)
         );
end COMPON_2;

architecture COMPON_2_arch of COMPON_2 is

component DEM2_COM
    port(
         DIN: in STD_LOGIC;
         S:   in STD_LOGIC;
         Y:   out STD_LOGIC_VECTOR (0 to 1)
        );
end component;

signal X: STD_LOGIC_VECTOR (0 to 1);	
begin
element1: DEM2_COM port map (DIN,S(1),X);
element2: DEM2_COM port map (X(0),S(0),Y(0 to 1));
element3: DEM2_COM port map (X(1),S(0),Y(2 to 3));  
end COMPON_2_arch;