ver1.chp

VHDL子程序集,包括各种例程资料以及源码.

=========
Chip ver1
=========

Summary Information:
--------------------
Type: Initial implementation
Source: out-of-date
Status: 1 errors, 1 warnings, 1 messages

Target Information:
-------------------
Vendor: Xilinx
Family: XC4000XL
Device: 4005XLPC84
Speed: xl-09

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 0
Number of latches: 0

Chip Design Hierarchy:
----------------------
MOORE_1: defined in c:\book\moore_1\moore_1\moore_1.vhd

Primitive reference count:
--------------------------
AND           1
SEQ           2

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00  100.00     RESET                

Timing Groups:
--------------
                                                                             
                                                                             
Name                           Description                                   
...........................................................................
(I)                            Input ports                                   
(O)                            Output ports                                  
(HL,RESET)                     Latched by high-value of RESET                

Timing Path Groups:
-------------------
                                                          Required  Estimated 
                                                          Delay     Delay     
From                         To                           (ns)      (ns)      
..........................................................................
(HL,RESET)                   (O)                           10.00     -1.00    

Input Port Timing:
------------------
                               Required   Estimated                            
Port                           Delay      Slack                                
Name                           (ns)       (ns)       To-Group                  
...........................................................................
CLK                              0.00      -1.00     (O)                       
RESET                            0.00      -1.00     (O)                       
X                                0.00      -1.00     (O)                       

Output Port Timing:
-------------------
                               Required   Estimated                            
Port                           Delay      Slack                                
Name                           (ns)       (ns)       From-Group                
...........................................................................
F                               10.00      -1.00     (HL,RESET)