moore_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 55 行

--******************************
--*        Parity Checker      *
--*     Filename : MOORE_1     *
--******************************
        
library IEEE;
use IEEE.std_logic_1164.all;

entity MOORE_1 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          X:     in STD_LOGIC;
          Z:     out STD_LOGIC
         );
end MOORE_1;

architecture MOORE_1_arch of MOORE_1 is
type State is (S1,S0);
signal Present_State: State;
signal Next_State: State;
begin
BB: process (CLK,RESET)  
                       
begin
    if RESET ='1' then 
       Present_State <= S0;
    elsif CLK'event and CLK = '1' then
       Present_State <= Next_State;
    end if;
end process BB;  

AA:process (Present_State,X)

begin
    case Present_State is
         when S0 =>
            if X ='0' then
               Next_State <= S0;
            else
               Next_State <= S1;
            end if;
            Z <= '0';
         when S1 =>
            if X ='0' then
               Next_State <= S1;
            else
               Next_State <= S0;
            end if;
            Z <= '1';
    end case;
end process AA;

end MOORE_1_arch;