pack_all.vhd

VHDL子程序集,包括各种例程资料以及源码.

--**************************************
--*  PACKAGE DECLARATION (COMPONENT ,  *
--*    FUNCTION , PROCEDURE ......)    *
--*       Filename : PACK_ALL          *
--**************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

PACKAGE PACK_ALL  IS

--Data Type Declaration

type BYTE_BUS is array (7 downto 0) of std_logic; 
constant  REG:std_logic_vector := "00000001";
 
--Component Declaration
     
component HA_COM
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          S0: out STD_LOGIC; 
          C1: out STD_LOGIC
         );
end component; 

component OR_GATE
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          F: out STD_LOGIC
         );
end component;

--Function Declaration
                      
function MUL4 (
               I: std_logic_vector (0 to 3);
	       S: std_logic_vector (1 downto 0)
	      ) return std_logic;
function MUL2 (
               I: std_logic_vector (0 to 1);
               S: std_logic
	      ) return std_logic;
	      
--Procedure Declaration
	      	      
procedure DEMUL4 (
                  signal D: in std_logic;
                  signal S: in std_logic_vector(1 downto 0);
                  signal Y: out std_logic_vector(0 to 3)
                 );
procedure DEMUL2 (
                  signal D: in std_logic;
                  signal S: in std_logic;
                  signal Y: out std_logic_vector(0 to 1)
                 );
            
end PACK_ALL;

PACKAGE BODY PACK_ALL IS

--Function Body
 
function MUL4 (
               I: std_logic_vector (0 to 3);
	       S: std_logic_vector (1 downto 0)
	      ) return std_logic is 
         variable F: std_logic;
begin
    case S is
         when "00"   => F := I(0);
	 when "01"   => F := I(1);
	 when "10"   => F := I(2);
	 when "11"   => F := I(3);
	 when others => null;
	end case;
    return F;   
end MUL4;

function MUL2 (
               I: std_logic_vector (0 to 1);
               S: std_logic
	      ) return std_logic is
         variable F: std_logic;
begin 
    case S is
         when '0'    => F := I(0);
         when '1'    => F := I(1);
         when others => null;
    end case;
    return F;   
end MUL2;

--Procedure Body
            
procedure DEMUL4 (
                  signal D: in std_logic;
                  signal S: in std_logic_vector(1 downto 0);
                  signal Y: out std_logic_vector(0 to 3)
                 ) is
begin
    case S is
         when "00"   => Y <= D & "111";
         when "01"   => Y <= '1' & D & "11";
         when "10"   => Y <= "11" & D & '1';
         when others => Y <= "111" & D;
    end case;
end DEMUL4;

procedure DEMUL2
            (signal D :in std_logic;
             signal S :in std_logic;
             signal Y :out std_logic_vector(0 to 1)
            ) is  
            
begin
    case S is
         when '0'    => Y <= D & '1';
         when others => Y <= '1' & D;
    end case;
end DEMUL2;
                              
end PACK_ALL;