gratobin.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 30 行

--***********************************
--*   Gray Code To Binary Convert   *
--*       Filename : GRATOBIN       *
--***********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity GRATOBIN is
    port (
          G: in STD_LOGIC_VECTOR (0 to 7);
          B: out STD_LOGIC_VECTOR (0 to 7)
         );
end GRATOBIN;

architecture GRATOBIN_arch of GRATOBIN is
signal TEMP: STD_LOGIC_VECTOR (0 to 7);
begin
process (G,TEMP)

begin
    TEMP(7) <= G(7);
    for i in 6 downto 0 loop
        TEMP(i) <= TEMP(i+1) xor G(i);
    end loop;  
    B <= TEMP;  
end process;  
   
end GRATOBIN_arch;