~~hier~~.tmp

VHDL子程序集,包括各种例程资料以及源码.

#BLOCK \ \ \ 0
#SIG CLK 0
#SIG CLK_BUFGPed 0
#SIG N115 0
#SIG N116 0
#SIG N72 0
#SIG N73 0
#SIG N74 0
#SIG N_Q3 1
#SIG N_Q2 1
#SIG N_Q1 1
#SIG N_Q0 1
#SIG N_RESET 0
#SIG N_UP_DOWN 0
#SIG Q3 2
#SIG Q2 2
#SIG Q1 2
#SIG Q0 2
#SIG RESET 0
#SIG syn232 0
#SIG UP_DOWN 0
#SIG SimGlobalReset 0
#COMP 0 C66 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C67 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C68 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C69 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C70 LUT4
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT I3 i 0
#PORT O o 0
#COMP 0 C71 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C72 BUFGP
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<0> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<1> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<2> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<3> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_RESET IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_UP_DOWN IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 Q_reg<0> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<1> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<2> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<3> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0