updown4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 37 行

--***************************
--*  4 Bit UP DOWN Counter  *
--*  Filename : UPDOWN4     *
--***************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity UPDOWN4 is
    port (
          CLK:      in STD_LOGIC;
          RESET:    in STD_LOGIC;
          UP_DOWN : in STD_LOGIC;
          Q:        inout STD_LOGIC_VECTOR (0 to 3)
         );
end UPDOWN4;

architecture UPDOWN4_arch of UPDOWN4 is

begin
process (CLK,RESET,Q)
    
begin
    if RESET = '0' then
       Q <= "0000";
    elsif CLK'event and CLK = '1' then
       if UP_DOWN = '1' THEN 
          Q <= Q + 1;
       else
          Q <= Q - 1;
       end if;  
    end if;  
end process;

end UPDOWN4_arch;