srl4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 37 行

--***********************************
--* 4 Bit Shift Right Left Register *
--*        Filename : SRL4          *
--***********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity SRL4 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          MODE : in STD_LOGIC;
          DIN :  in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (3 downto 0)
         );
end SRL4;

architecture SRL4_arch of SRL4 is

begin
process (CLK,RESET,Q)

begin   
     if RESET = '0' then 
        Q <= "0000";
     elsif CLK'event and CLK = '1' then
        if MODE = '1' then   
           Q <= DIN & Q (3 downto 1);
        else
           Q <= Q (2 downto 0) & DIN;
        end if;  
     end if;  
end process;  
      
end SRL4_arch;