for_3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 35 行

--*********************************
--*   4 Bit Shift Right Register  * 
--*        Filename : FOR_3       * 
--*********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity FOR_3 is
    port (
          CLK:   in STD_LOGIC;
          DIN:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (0 to 3)
         );
end FOR_3;

architecture FOR_3_arch of FOR_3 is

begin
process (CLK,RESET)

begin   
    if RESET = '0' then 
       Q <= "0000";
    elsif CLK'event and CLK = '1' then
       Q(0) <= DIN;     
       for i in 1 to 3 loop
           Q(i) <= Q(i-1);
       end loop;    
    end if;
end process;
        
end FOR_3_arch;