generat2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 37 行

--*****************************************
--* 8 Bit Shift Right Register (GENERATE) *
--*   Component : S_R_GENE , DFF (Nest)   *
--*          Filename : GENERAT2          *
--*****************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity GENERAT2 is
    port (
          DIN:   in STD_LOGIC;
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     out STD_LOGIC_VECTOR (0 to 7) 
         );
end GENERAT2;

architecture GENERAT2_arch of GENERAT2 is

component S_R_GENE
        generic (number: integer range 1 to 31);
        port
            (
             DIN:   in STD_LOGIC;
             CLK:   in STD_LOGIC;
             RESET: in STD_LOGIC;
             Q:     out STD_LOGIC_VECTOR (0 to number-1) 
            );
end component S_R_GENE;
    
begin
element:S_R_GENE
        generic map (8)
        port map (DIN,CLK,RESET,Q);
end GENERAT2_arch;