~~hier~~.tmp

来自「VHDL子程序集,包括各种例程资料以及源码.」· TMP 代码 · 共 98 行

#BLOCK \ \ \ 0
#SIG CLK 0
#SIG CLK_BUFGPed 0
#SIG DIN 0
#SIG N_DIN 0
#SIG N_Q7 1
#SIG N_Q6 1
#SIG N_Q5 1
#SIG N_Q4 1
#SIG N_Q3 1
#SIG N_Q2 1
#SIG N_Q1 1
#SIG N_Q0 1
#SIG N_RESET 0
#SIG Q7 2
#SIG Q6 2
#SIG Q5 2
#SIG Q4 2
#SIG Q3 2
#SIG Q2 2
#SIG Q1 2
#SIG Q0 2
#SIG RESET 0
#SIG SimGlobalReset 0
#COMP 0 C71 BUFGP
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<0> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<1> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<2> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<3> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<4> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<5> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<6> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<7> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_RESET IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 element/DFF0_0/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_1/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_2/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_3/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_4/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_5/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_6/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 element/DFFO_7/Q_reg FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0