s_r_gene.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*********************************
--*    Shift Right (GENERATE)     *
--*     Using Component : DFF     *
--*      Filename : S_R_GENE      *
--*********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity S_R_GENE is
    generic (number: integer range 1 to 31 := 1);
    port (
          DIN:   in  STD_LOGIC;
          CLK:   in  STD_LOGIC;
          RESET: in  STD_LOGIC;
          Q:     out STD_LOGIC_VECTOR (0 to number -1)
         );
end S_R_GENE;

architecture S_R_GENE_arch of S_R_GENE is
signal REG:std_logic_vector(1 to number);

component DFF
       port (
             D:     in STD_LOGIC;
             CLK:   in STD_LOGIC;
             RESET: in STD_LOGIC;
             Q:     out STD_LOGIC
            );
end component;
            
begin
LOP:   for I in 0 to number-1 generate       
first:     if I = 0 generate
DFF0:         DFF port map (DIN,CLK,RESET,REG(I+1));
           end generate;
OTHER:     if I > 0 and I < number  generate
DFFO:         DFF port map (REG(I),CLK,RESET,REG(I+1));                   
           end generate;   
       end generate LOP;
       Q <= REG;     
end S_R_GENE_arch;