proced_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 34 行

--************************************
--*   16 Bit Parity ODD Generator    *
--*   (PROCEDUER IN ARCHITECTURE)    *
--*       Filename : PROCED_1        *
--************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity proced_1 is
    port (
          I:      in STD_LOGIC_VECTOR (0 to 15);
          Parity: out STD_LOGIC
         );
end proced_1;

architecture Proced_1_arch of Proced_1 is

procedure odd (signal I: in std_logic_vector ;
  	       signal P: out std_logic
  	      ) is
          variable PO:std_logic; 
begin 
    PO := '1';
    for K in i'range loop
        PO := PO xor I(K);
    end loop;
    P <= PO;
end odd;
   
begin
    odd(I,Parity);
end proced_1_arch;