boolean1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--**********************************
--*   2 To 4 Decoder Active HIGH   *
--*   Using Boolean Algebra (1)    *
--*      Filename : BOOLEAN1       *
--********************************** 

library IEEE;
use IEEE.std_logic_1164.all;

entity BOOLEAN1 is
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          Y: out STD_LOGIC_VECTOR (0 to 3)
          );
end BOOLEAN1;

architecture BOOLEAN1_arch of BOOLEAN1 is

begin
    Y(0) <= not A and not B;
    Y(1) <= not A and B;
    Y(2) <= A and not B;
    Y(3) <= A and B; 
end BOOLEAN1_arch;