gener_2.vhd

VHDL子程序集,包括各种例程资料以及源码.

--**********************************
--*   16 Bit XOR GATE (GENERIC)    *
--*   Using  COMPONENT : GENER_1   *
--*       Filename : GENER_2       *
--**********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity GENER_2 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 15);
          F: out STD_LOGIC
         );
end GENER_2;

architecture GENER_2_arch of GENER_2 is

component GENER_1
     generic (number: integer range 1 to 31); 
     port
         (I: in std_logic_vector(1 to number);
          F: out std_logic
         );
end component;             

begin
    Parity: GENER_1 
          generic map (16)
          port map (I,F);
end GENER_2_arch;