gener_1.vhd

VHDL子程序集,包括各种例程资料以及源码.

--************************************
--*   XOR GATE COMPONENT (GENERIC)   *
--*       Filename : GENER_1         *
--************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity GENER_1 is
    generic (number: integer range 1 to 31 := 8);  
    port (
          I: in STD_LOGIC_VECTOR (1 to number);
          F: out STD_LOGIC
         );
end GENER_1;

architecture GENER_1_arch of GENER_1 is

begin
process (I) 
variable Y: std_logic;
begin
    Y := '0';
    for j in I'left to I'right loop
        Y := Y xor I(j);
    end loop;
    F <= Y;
end process;
 
end GENER_1_arch;