adder1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 25 行

--*******************************************
--* 1 Bit Full Adder Using Boolean Algebra  *
--*           Filename : ADDER1             *
--*******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity ADDER1 is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          C0: in STD_LOGIC;
          S0: out STD_LOGIC;
          C1: out STD_LOGIC
         );
end ADDER1;

architecture ADDER1_arch of ADDER1 is

begin
    S0 <= X0 xor Y0 xor C0;
    C1 <= (X0 and C0) or (X0 and Y0) or (C0 and Y0);
end ADDER1_arch;