moore_2.twr

VHDL子程序集,包括各种例程资料以及源码.

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Xilinx TRACE, Version D.19
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

trce moore_2.ncd moore_2.pcf -e 3 -o moore_2.twr

Design file:              moore_2.ncd
Physical constraint file: moore_2.pcf
Device,speed:             xc2s100,-6 (PREVIEW 1.12 2000-05-03)
Report level:             error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis
 18 items analyzed, 0 timing errors detected.
 Minimum period is   3.552ns.
 Maximum delay is   8.591ns.
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================================================================================
Timing constraint: Default net enumeration
 9 items analyzed, 0 timing errors detected.
 Maximum net delay is   1.421ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
X              |    1.686(R)|    0.000(R)|
---------------+------------+------------+

Clock CLK to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
Z              |   10.258(R)|
---------------+------------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
CLK            |    3.552|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 18 paths, 9 nets, and 20 connections (100.0% coverage)

Design statistics:
   Minimum period:   3.552ns (Maximum frequency: 281.532MHz)
   Maximum combinational path delay:   8.591ns
   Maximum net delay:   1.421ns


Analysis completed Fri Nov 08 10:26:29 2002
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