moore_2.par

VHDL子程序集,包括各种例程资料以及源码.

Release 3.1i - Par D.19

Fri Nov 08 10:26:00 2002

par -w -ol 2 -d 0 map.ncd moore_2.ncd moore_2.pcf


Constraints file: moore_2.pcf

Loading device database for application par from file "map.ncd".
   "MOORE_2" is an NCD, version 2.32, device xc2s100, package tq144, speed -6
Loading device for application par from file 'v100.nph' in environment
c:/Fndtn.
Device speed data version:  PREVIEW 1.12 2000-05-03.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             3 out of 92      3%

   Number of SLICEs                    3 out of 1200    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Placement phase. REAL time: 9 secs 
Finished initial Placement phase. REAL time: 9 secs 
Starting the placer. REAL time: 9 secs 
Placement pass 1 .
Placer score = 240
Optimizing ... 
Placer score = 165
Starting IO Improvement.  REAL time: 9 secs 
Placer score = 165
Finished IO Improvement.  REAL time: 9 secs 

Placer completed in real time: 9 secs 

Writing design to file "moore_2.ncd".

Total REAL time to Placer completion: 9 secs 
Total CPU time to Placer completion: 10 secs 

0 connection(s) routed; 20 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 11 secs 
Starting iterative routing. 
Routing active signals.
...
End of iteration 1 
20 successful; 0 unrouted; (0) REAL time: 12 secs 
Constraints are met. 
Total REAL time: 12 secs 
Total CPU  time: 12 secs 
End of route.  20 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 12 secs 
Total CPU time to Router completion: 13 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 115


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.003 ns
   The Maximum Pin Delay is:                               1.421 ns
   The Average Connection Delay on the 10 Worst Nets is:   0.737 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           6          14           0           0           0           0

Writing design to file "moore_2.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 13 secs 
Total CPU time to PAR completion: 13 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.